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Freescale Semiconductor /MK61F15WS /DDR /CR04

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Interpret as CR04

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0TBINT0RESERVED0TRRD0RESERVED0TRC0RESERVED 0TRASMIN

Description

DDR Control Register 4

Fields

TBINT

Time Burst Interrupt Interval
RESERVED

Reserved
TRRD

no description available
RESERVED

Reserved
TRC

no description available
RESERVED

Reserved
TRASMIN

Time RAS Minimum

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data